1. Field of the Invention
The present invention relates to a packaging design system for an LSI circuit, and provides advantages in designing LSI circuit that were not previously available.
2. Description of the Related Art
In general, an LSI (Large Scale Integrated) circuit includes a plurality of gates (AND gates, OR gates, flip-flop circuits, registers, etc.). When transferring data among a plurality of gates, the data are transferred in response to clock signals that are input into the gates. In this case, in order to synchronizes the data at one output terminal with other data at other output terminals, it is necessary that all propagation delays (below, path delays) of the clock signals are the same among all gates.
In a conventional packaging design of an LSI circuit, two representative design methods are proposed in order to realize the minimum path delay. In a first method, a plurality of gates are arranged at locations where the path delays are previously known. In a second method, all "net lengths" ("net" refers to wires connecting gates) between gates are determined taking the path delay into consideration.
However, it is very difficult to employ both the first and second methods because a recently LSI circuits are formed of very many gates (perhaps more than several thousand gates), with very high packaging density, and very fine wiring patterns. Accordingly, it is very difficult to realize an LSI circuit having the minimum path delay. Minimum path delay can be expressed by a minimum skew value, and in general, the minimum skew value means the difference between a standard path delay and an actual path delay.
Further, in a conventional placement process for gates (so-called "floor plan") used in a CAD system, when a circuit designer prepares the gate placement data which are used as original data in the design of the LSI circuit, the registration processes of blocks formed by a plurality of basic gates (a block is called a "macro" in the CAD system) are separated from the preparation processes of placement areas. Finally, these processes are automatically performed using the CAD system.
However, since the blocks to be registered are previously known for clock transfer routes, scanning routes and OSL (Only Scan Latch) routes (the OSL route is used for only a test of the circuit), and since the placement areas are considered for all areas of the LSI chip, it is not necessary to separate these processes taking propagation delay of data within the LSI circuit into consideration.